Integrated circuits such as microprocessors, microcomputers, microcontrollers, and the like comprise a number of functional units (e.g., memories, input interfaces, output interfaces, arithmetic and logic units, etc.) that are interconnected and share information. Information in the form of digital signals typically is shared amongst functional units in a parallel manner via transmission over a plurality of shared signal lines termed a bus.
To transmit or drive digital signals on a bus, each functional unit is coupled to each signal line of the bus via a driver that provides the voltage and current levels required to drive the signal line. Thus, each functional unit has at least one driver per signal line.
Most drivers are three-state drivers that comprise an input terminal for receiving digital signals from the functional unit, an output terminal for outputting a buffered version of the digital signals consistent with the voltage/current requirements of the bus, and an enable terminal for selectively enabling/disabling the driver. A driver coupled to a signal line thus can pull the signal line to a low voltage (e.g., zero volts) logic state or a "low state", can pull the signal line to a high voltage (e.g., 3.5 volts, 5 volts, etc.) logic state or "high state", or can leave the signal line in a floating or "high impedance" state when the driver is disabled, for example, via lack of an enable signal on the driver's enable terminal.
Because multiple functional units share a bus, multiple drivers often are coupled to each signal line. During normal bus operation, only one driver at a time drives a signal line. Nonetheless, under certain circumstances multiple drivers can attempt to simultaneously drive a signal line (i.e., bus contention). Bus contention is problematic because it leads to uncertainty as to the logic state of the signal line (e.g., when one driver drives a signal line with a low voltage while another driver drives the signal line with a high voltage), and because excessive current and voltage levels may be produced on a signal line that can damage driver circuitry and/or the various functional units connected to the signal line.
FIG. 1A is a schematic view of a conventional bus control logic circuit 100 designed to avoid bus contention on a signal line 102 of a bus (not shown). Specifically, bus control logic circuit 100 comprises a driver decoder 104 having a first and a second address input terminal 106a, 106b, respectively, and having a plurality of output terminals 108a-d. When the bus control logic circuit 100 is used to control a plurality of drivers 110a-d coupled to the signal line 102, each output terminal 108a-d of the driver decoder 104 is connected, respectively, to an enable input terminal 112a-d of each the driver 110a-d.
The driver decoder 104 is configured so that only one output terminal 108a-d at time is at a high state, the logic state required to enable the drivers 110a-d. Each output terminal 108a-d is placed at the high state through a unique combination of high or low states present on the first and second address input terminals 106a, 106b. TABLE 1A shows the logic state of each output terminal 108a-d for each combination of high or low states present on the first and second address input terminals 106a, 106b. A low state is represented by 0 and a high voltage state is represented by 1.
TABLE 1A __________________________________________________________________________ FIRST SECOND ADDRESS ADDRESS INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL 106a 106b 108a 108b 108c 108d __________________________________________________________________________ 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 __________________________________________________________________________
In addition to an enable input terminal 112a-d, each driver 110a-d has a data input terminal 114a-d, respectively, and a driver output terminal 116a-d, respectively. Each driver output terminal 116a-d of each driver 110a-d is coupled to the signal line 102 as shown in FIG. 1A.
Each data input terminal 114a-d of each driver 110a-d is connected to a unique functional unit (not shown) and allows the functional unit to drive digital signals over the signal line 102 via the respective driver. For instance, assuming the first driver 110a is enabled (via a high state on the enable input terminal 112a), a functional unit A (not shown) coupled to the first driver 110a may drive data on the signal line 102 by outputting digital signals to the data input terminal 114a of the first driver 110a, thereby causing the first driver 110a to output corresponding digital signals on the driver output terminal 116a, whereas if the second driver 110b is enabled, a functional unit B (not shown) coupled to the second driver 110b may drive digital signals on the signal line 102 by outputting the digital signals to the data input terminal 114b of the second driver 110b thereby causing the second driver 110b to output corresponding digital signals on the driver output terminal 116b, etc.
Also shown in FIG. 1A are a soft driver 118 and a buffer 126. As with the drivers 110a-d, the soft driver 118 has an enable input terminal 120, a driver output terminal 122 coupled to the signal line 102, and a data input terminal 124. The buffer 126 has a buffer input terminal 128 coupled to the signal line 102 and a buffer output terminal 130. In operation, when enabled, the soft driver 118 pulls the signal line 102 to a high or a low state based on a logic state input to the data input terminal 124, and the buffer 126 monitors the logic state of the signal line 102. As described below, both the soft driver 118 and the buffer 126 are used for testing the bus control logic circuit 100.
During normal operation, a controller (not shown) such as a microprocessor or a dedicated controlling mechanism regulates functional unit access to the signal line 102 via the bus control logic circuit 100 by controlling the address signals provided to the first and second address input terminals 106a, 106b of the driver decoder 104. For example, if a functional unit is to drive digital signals on the signal line 102 via the data input terminal 114a, the controller must drive both the first address input terminal 106a and the second address input terminal 106b to a low state so that the output terminal 108a outputs a high state (TABLE 1A). The high state on the output terminal 108a drives the enable input terminal 112a of the first driver 110a, enabling the first driver 110a. Thereafter, the functional unit may drive digital signals on the signal line 102 by driving the data input terminal 114a of the first driver 110a with the digital signals so that the first driver 110a outputs (via the driver output terminal 116a) corresponding digital signals on the signal line 102. As shown in TABLE 1A, when the first driver 110a is enabled, the enable input terminal 112b-d of every other driver 110b-d is driven to a low state so that drivers 110b-d are disabled. The remaining drivers 110b-d may be similarly used by other functional units to drive digital signals on the signal line 102. Because the driver decoder 104 only allows one of the drivers 110a-d at a time to be enabled, when the bus control logic circuit 100 functions properly, bus contention does not occur.
When the bus control logic circuit 100 fails to operate properly, however, three types of bus faults can exist:
1. no driver is enabled in response to address signals present on the address input terminals 106a-b (i.e., a "no-connection fault");
2. the wrong driver is enabled in response to address signals present on the address input terminals 106a-b (i.e., a "cross-connection fault"); and
3. in addition to the intended driver, a second driver is enabled and drives the signal line 102 in response to address signals present on the address input terminals 106a-b (i.e., a "bus-contention stuck fault").
Fortunately, the bus control logic circuit 100 can be tested for the first two bus faults, the no-connection and the cross-connection bus faults. Testing for these two types of bus faults typically is performed as a quality assurance measure during the manufacture of integrated circuits employing the bus control logic circuit 100.
To test for a no-connection fault within the bus control logic circuit 100, the soft driver 118 is used to either pull the signal line 102 to a high state or to a low state by driving the data input terminal 124 with the desired logic state and by enabling the soft driver 118 via the enable input terminal 120 (so as to drive the signal line 102 to the desired logic state). Because the driver 118 is a "soft" driver, the drivers 110a-d can override a signal line logic state set by the soft driver 118. Accordingly, to test for a no-connection fault, each driver 110a-d is sequentially enabled and caused to drive the signal line 102 with a logic state different from the logic state set by the soft driver 118. The logic state of the signal line 102 is monitored by the buffer 126. If any driver 110a-d is unable to change the logic state of the signal line 102 as set by the soft driver 118, the presence of a no-connection bus fault within the portion of the logic circuitry controlling that driver (i.e., the driver's driver circuitry) is confirmed.
The presence of a cross-connection bus fault within the bus control logic circuit 100 can be determined without the use of the soft driver 118. To test for a cross-connection bus fault within the driver circuitry of the first driver 110a, the first and second address input terminals 106a, 106b are driven with the address signals corresponding to the address of the first driver 110a (e.g., 0, 0), and the data input terminal 114a is set to drive a first logic state on the signal line 102 if the first driver 110a is enabled. The remaining drivers 110b-d are set to drive a second, opposite logic state on the signal line 102, and the logic state of the signal line 102 is monitored via the buffer 126. If the logic state of the signal line 102 is determined to be the first logic state, then no cross-connection bus fault exists with regard to the driver circuitry of the first driver 110a. Likewise, if the logic state of the signal line 102 is determined to be the second logic state, then a cross-connection bus fault exists with regard to the driver circuitry of the first driver 110a. The driver circuitry for the remaining drivers 110b-d may be tested in the same manner for cross-connection bus faults.
As stated, the third type of bus fault is the bus-contention stuck fault. A bus-contention stuck fault arises when an input terminal of a logic gate within driver circuitry is "stuck" or pinned at one logic state due to a manufacturing defect. FIG. 1B is a schematic view of a portion of the logic circuitry within a typical NOR gate decoder, and is useful for explaining stuck fault bus contention.
The portion of the logic circuitry shown comprises a first NOR gate 132 having a first input terminal 132a, a second input terminal 132b and an output terminal 132c, and a second NOR gate 134 having a first input terminal 134a, a second input terminal 134b and an output terminal 134c. The circuitry further comprises a first address input terminal 138, a second address input terminal 140, and an inverter 136 having an input terminal 136a and an output terminal 136b. The various components of the portion of the logic circuitry are connected as follows: the first address input terminal 138 is connected to the first input terminal 132a of the first NOR gate 132 and to the first input terminal 134a of the second NOR gate 134; the second address input terminal 140 is connected to the input terminal 136a of the inverter 136 and to the second input terminal 132b of the first NOR gate 132; and the output terminal 136b of the inverter 136 is connected to the second input terminal 134b of the second NOR gate 134. When the circuitry of FIG. 1B is employed to control drivers, the output terminals 132c and 134c of each NOR gate 132 and 134, respectively, each couple to an enable input terminal of a unique driver so as to allow each unique driver to be selectively enabled as described below.
To aid in understanding the operation of the logic circuitry of FIG. 1B, the truth table for a NOR gate having inputs A, B and output C is shown in TABLE 1B:
TABLE 1B ______________________________________ A B C ______________________________________ 0 0 1 0 1 0 1 0 0 1 1 0 ______________________________________
As seen in TABLE 1B, the output of a NOR gate is in a high state only when both inputs are in a low state.
With reference to FIG. 1B, absent a bus-contention stuck fault, when both the address input terminals 138 and 140 are driven to a low state (e.g., by a functional unit, or by a controller), input terminals 132a, 132b and 134a are driven to a low state, while input terminal 134b is driven to a high state via the inverter 136. Because both input terminals 132a-b are driven to a low state, the output terminal 132c of the first NOR gate 132 is driven to a high state, enabling any driver connected thereto. Further, because both input terminals 134a-b are not driven to a low state, the output terminal 134c of the second NOR gate 134 is driven to a low state, disabling any driver connected thereto.
Similarly, absent a bus-contention stuck fault, when the address input terminal 138 is driven to a low state and the address input terminal 140 is driven to a high state, input terminals 132a, 134a and 134b (via the inverter 136) are driven to a low state, and the input terminal 132b is driven to a high state. Accordingly, the output terminal 132c of the first NOR gate 132 is driven to a low state (disabling any driver connected thereto) and the output terminal 134c of the second NOR gate 134 is driven to a high state (enabling any driver connected thereto). Thus, no matter what logic states exist on the address input terminals 138 and 140, no more than one driver is enabled at a time and bus contention does not occur.
However, when a bus-contention stuck fault is present two drivers can be enabled simultaneously. For example, assume a bus-contention stuck fault (F) is present on the input terminal 132b of the first NOR gate 132. The bus-contention stuck fault (F) causes the logic state of the input terminal 132b to remain at a low state regardless of the logic state present on the address input terminal 140. As such, when the address input terminal 138 is driven to a low state and the address input terminal 140 is driven to a high state, all input terminals 132a, 132b, 134a and 134b are driven to a low state. Both the output terminal 132c and the output terminal 134c therefore are driven to a high state, enabling multiple drivers and resulting in stuck-fault bus contention.
While the bus control logic circuit 100 can be tested for no-connection and for cross-connection bus faults (as previously described), normally it cannot be tested for stuck-fault bus contention. Because the signal line 102, the drivers 110a-d, and the bus control logic circuit 100 typically are embedded within an integrated circuit, the voltage and current levels present on the signal line 102 cannot be directly observed. The only measure of the voltage and current levels present on the signal line 102 is an indirect, buffered version provided by a buffer such as the buffer 126. That is, even though a bus-contention stuck fault may in some cases produce a substantially larger-than-normal current level on the signal line 102 (e.g., when a first driver drives the signal line 102 to a low voltage level while another driver drives the signal line 102 to a high voltage level), the buffer 126 provides no information about the actual current level present on the signal line 102. The buffer 126 merely provides an indication that the voltage level present on the signal line 102 is low enough to be considered a low voltage logic state or is high enough to be considered a high voltage logic state. Thus, bus contention (e.g., due to a bus-contention stuck fault) within the bus control logic circuit 100 normally cannot be observed.
Accordingly, a need exists for bus control logic circuitry that can be tested for bus-contention stuck faults as well as for no-connection and cross-connection faults. Such bus control logic circuitry will improve significantly the quality assurance testing of integrated circuits containing bus systems.